Home

5-Stage Pipelined RISC-V CPU Written from Scratch in Verilog

If you are not able to see the report above, please download the PDF to view it: Download PDF.

Winner of Apple-Sponsored Project: FPGA Outstanding Project Design Award

Key Topics:

  • FPGA CPU Design
  • Memory-Mapped Peripherals
  • Fully Functional/Customizable Audio Synthesizer
  • Global branch prediction optimization